1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication, and more specifically to deep sub-micron fabrication of low resistance polycide structures.
2. Description of the Related Art
The drive to integrate ever-increasing numbers of transistors onto a single integrated circuit necessitates the fabrication of increasingly smaller MOSFET (metal oxide semiconductor field effect transistor) and interconnection structures in semiconductor devices. Nowhere is this more true than in memory circuits. Current process technology has allowed the reduction of the line size (the width of conductive paths in an integrated circuit) to the deep sub-micron ( less than 0.2 micron) level. At this level, the resistance of the gate stack, also known as a gate electrode (the conductive structure that forms the gate of a transistor), and interconnection layers, becomes a limiting factor in the speed of the device. Accordingly, it has become increasingly important to use materials with the lowest possible resistance to form gate stacks and interconnection layers.
Historically, polysilicon has been used as the material for gate stacks because of many advantageous properties including good thermal stability and low resistance. Polysilicon is especially well suited for the interface to gate oxide layers in gate stacks. Polysilicon sheet resistances of 15-20 ohms/sq m may be achieved using known techniques. However, resistances even this low become significant in deep sub-micron fabrication.
Refractory metal silicides and near-noble metal silicides are well known to those of skill in the art of semiconductor fabrication. The low sheet resistance (as low as 3-5 ohms/sq m) of such metal silicides and the ability to use such metal silicides with conventional semiconductor techniques has led to increasing use of these materials in semiconductor devices. For example, titanium disilicide (TiSi2) is known to have a low sheet resistance and is widely used for gate stacks and interconnection layers in semiconductor devices.
However, refractory and near-noble metal silicides suffer from a serious drawback which makes them unsuitable for certain applications. Many semiconductor fabrication processes, especially memory cell fabrication processes, require high temperature (approximately 800xc2x0 C. to 1000xc2x0 C. or above) annealing, reoxidation and activation cycles. At high temperatures, refractory and near-noble metal silicides suffer from the well-known problem of thermal agglomeration. Silicides become unstable and begin to agglomerate, or bubble, at high temperatures, especially along boundaries with polysilicon or SiO2, which causes dislocations or discontinuities in the silicide at the boundaries. Although the exact mechanisms of agglomeration are complex and varied, it is widely accepted that a major contributing factor to agglomeration is the action of polysilicon grain boundaries as rapid diffusion routes for transporting silicon which diffuses out of polysilicon or SiO2 during high temperature processing such as annealing. Thus, most refractory and near noble metal silicides cannot be used alone in gate stacks and other structures in which they adjoin polysilicon or SiO2 when high temperature processing is required.
The aforementioned agglomeration problem associated with high temperature processing of most refractory metal silicides has led to the creation of modified structures consisting of 1) a polysilicon layer at a polysilicon or SiO2 boundary (such as the gate oxide in a gate stack), 2) a diffusion barrier layer, and 3) a refractory or near noble metal silicide layer. The diffusion barrier layer prevents the diffusion of metals from the metal silicide layer into the polysilicon layer during the formation of the metal silicide layer and does not itself agglomerate at its interface with polysilicon or SiO2. Such structures are known as polycides and, when used to form source/drain or gate electrodes, as salicides (self aligned silicides). As used herein, the term polycide is used generically to refer to both polycide and salicide structures. These structures combine the advantages of the good interface provided by polysilicon with the low resistance of metal silicides while avoiding the thermal agglomeration problem associated with metal silicide interfaces caused by high temperature processing.
Diffusion barrier layers for polycide structures are disclosed in U.S. Pat. Nos. 5,818,092 (the xe2x80x9c""092 patentxe2x80x9d) and 5,543,362 (the xe2x80x9c""362 patentxe2x80x9d). The ""092 teaches a barrier layer composed of an oxide, silicon nitride, an oxynitride, or a thin metal layer such as titanium nitride or tantalum nitride. Of these materials, only titanium nitride or tantalum nitride are conductive and therefore only these materials may be used when conductivity is required (oxides, silicon nitride and oxynitrides are used in the formation of floating gatesxe2x80x94gates that are electrically isolatedxe2x80x94in applications such as flash memory devices). The ""362 patent discloses diffusion barrier layers of titanium nitride, boron nitride, pure refractory metals, and intermettalic alloys of tungsten, platinum and cobalt. Experience has shown that using any of these known materials is problematic because these materials tend to oxidize during high temperature processes, such as source/drain reoxidation, that are typically performed during DRAM fabrication.
Thus, what is needed is a conductive polycide structure that is tolerant of high temperature processing and that exhibits good self-passivation (resistance to oxidation).
The present invention provides a polycide structure comprising a lower polysilicon layer, a conductive barrier layer comprising ZSix, where x greater than 2 and Z is either tungsten, molybdenum or tantalum, and an upper refractory or near-noble metal silicide layer. Although ZSix (x greater than 2, Z=W, Ta, or Mo) are refractory metal silicides, experience has shown that they exhibit good thermal stability and do not agglomerate at polysilicon or SiO2 interfaces even at high temperatures. The present invention is especially well suited for use in gate stacks and/or interconnection layers in semiconductor applications, especially memory circuits, where low resistance is necessary and high temperature processing steps are employed.